标题: 基于LPC2939设计的MCU USB接口技术 [打印本页] 作者: liyf 时间: 2012-1-18 00:44 标题: 基于LPC2939设计的MCU USB接口技术 LPC2939集成了两个TCM 的ARM968E-S CPU 核的MCU,工作频率高达125MHz,并集成了全速USb 2.0主/OTG/设备控制器,CAN和LIN,56kb SRAM,768kb闪存以及外接存储器接口,三个10位ADC,多个串行和并行接口.主要用在消费类电子,工业,医疗和通信市场.本文介绍了LPC2939主要特性, 方框图,以及各种USb,USb OTG接口方框图．LPC2939: ARM9 microcontroller with CAN, LIN, and USbThe LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz, Full-speed USb 2.0 Host/OTG/Device controller, CAN and LIN, 56 kb SRAM, 768 kb flash memory, external memory interface,three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC2939 has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling.LPC2939主要特性和优势:ARM968E-S processor running at frequencies of up to 125 MHz maximum.Multilayer AHb system bus at 125 MHz with four separate layers.On-chip memory:Two Tightly Coupled Memories (TCM), 32 kb Instruction (ITCM), 32 kb Data TCM (DTCM)Two separate internal Static RAM (SRAM) instances; 32 kb SRAM and 16 kb SRAM8 kb ETb SRAM, also usable for code execution and data768 kb high-speed flash program memory16 kb true EEPROM, byte-erasable/programmableDual-master, eight-channel GPDMA controller on the AHb multilayer matrix which can be used with the SPI interfaces and the UARTs, as well as for memory-to-memory transfers including the TCM memoriesExternal Static Memory Controller (SMC) with eight memory banks; up to 32-bit data bus; up to 24-bit address busSerial interfaces:USb 2.0 full-speed Host/OTG/Device controller with dedicated DMA controller and on-chip device PHYTwo-channel CAN controller supporting FullCAN and extensive message filteringTwo LIN master controllers with full hardware support for LIN communication. The LIN interface can be configured as UART to provide two additional UART interfaces.Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, modem control, and RS-485/EIA-485 (9-bit) supportThree full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;Tx FIFO and Rx FIFOTwo I2C-bus interfacesOther peripherals:One 10-bit ADC with 5.0 V measurement range and eight input channels with conversion times as low as 2.44 ?s per channelTwo 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide an additional 16 analog inputs with conversion times as low as 2.44 ?s per channel. Each channel provides a compare function to minimize interrupts.Multiple trigger-start option for all ADCs: timer, PWM, other ADC, and external signal inputFour 32-bit timers each containing four capture-and-compare registers linked to I/OsFour six-channel PWMs (Pulse-Width Modulators) with capture and trap functionalityTwo dedicated 32-bit timers to schedule and synchronize PWM and ADCQuadrature encoder interface that can monitor one external quadrature encoder32-bit watchdog with timer change protection, running on safe clockUp to 152 general-purpose I/O pins with programmable pull-up, pull-down, or bus keeperVectored Interrupt Controller (VIC) with 16 priority levelsUp to 22 level-sensitive external interrupt pins, including USb, CAN and LIN wake-up featuresConfigurable clock-out pin for driving external system clocksProcessor wake-up from power-down via external interrupt pins and CAN or LIN activityFlexible Reset Generator Unit (RGU) able to control resets of individual modulesFlexible Clock-Generation Unit (CGU) able to control clock frequency of individual modules:On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to provide a Safe_Clock source for system monitoringOn-chip crystal oscillator with a recommended operating range from 10 MHz to 25 MHz. PLL input range 10 MHz to 25 MHz.On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHzGeneration of up to 11 base clocksSeven fractional dividersSecond, dedicated CGU with its own PLL generates USb clocks and a configurable clock outputHighly configurable system Power Management Unit (PMU):clock control of individual modulesallows minimization of system operating power consumption in any configurationStandard ARM test and debug interface with real-time in-circuit emulatorboundary-scan test supportedETM/ETb debug functions with 8 kb of dedicated SRAM also accessible for application code and data storageDual power supply:CPU operating voltage: 1.8 V ? 5 %I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V208-pin LQFP package
图1.LPC2939方框图
图2.LPC2939自供电设备USb接口方框图
图3.LPC2939总线供电设备USb接口方框图
图4.LPC2939 USb OTG端口配置:USb端口1 OTG双任务设备,USb端口2主机
图5.LPC2939 USb OTG端口配置:USb端口1主机,USb端口2主机
图6.LPC2939 USb OTG端口配置:USb端口2设备,USb端口1主机
